The invention relates broadly to the trimming of monolithic semiconductor integrated circuit (IC) devices using the so-called zener zap approach. In U.S. Pat. No. 4,225,878 to Robert C. Dobkin, and assigned to the assignee of the present invention, a back-to-back zene diode configuration is disclosed. In my copending application Ser. No. 186,797 filed Sept. 12, 1980, and titled BILATERAL ZENER TRIM, an improved back-to-back zener diode structure is disclosed. Basically, a string of series resistors is connected to zener diodes so that each resistor has a parallel diode. When a particular diode is zapped, or shorted out, the associated resistor is shorted out and the string value reduced by that amount. By using back-to-back diodes, the number of IC chip pads is reduced and the zapping is determined by the polarity of the pulse as well as the pads being used. My above-identified application relates to a structure in which the forward biased diode in the pair is protected. It is intended that the protected structure be employed in practicing the present invention.
Clearly, in prior art zener zapping, the starting trim resistance is maximum and is reduced in steps as each diode is zapped. It would be desirable to start with a nominal mid-range resistance value with trimming acting to either raise or lower this value.